Ferroelectric capacitors or capacitor-like structures are of increasing interest in a number of integrated circuit applications. For example, as the feature size of DRAM memory cells is decreased in attempts to increase the density of DRAM based memories, the physical dimensions of the capacitors used to store the charge representing the data are also decreased. Since there is a minimum capacitance below which the DRAM cell will not operated satisfactorily, either a multilayer capacitor structure or a capacitor structure having an increased dielectric constant is needed. The former solution would substantially increase the cost of the memories; hence, there has been significant interest in utilizing capacitors with increased dielectric constants. Ferroelectric based capacitors based on lead zirconate titanate (PZT) that has been doped to be paraelectric at the operating temperature of the DRAMs have dielectric constants greater than 100. Hence, PZT-based capacitors are attractive candidates for replacing the conventional capacitors currently used in DRAMs.
Non-volatile memories based on PZT dielectric capacitors in which the dielectric is doped to be a ferroelectric at the operating temperature of the device have also attracted considerable interest because of the retention of the data in the absence of power. In addition, non-volatile memories based on a ferroelectric field effect transistor may also be used. Such a transistor structure is described in U.S. Pat. No. 5,070,385. This type of transistor may be viewed as a ferroelectric capacitor in which the top electrode is replaced by a semi-conductor layer having two contacts constructed thereon.
All of these memory cells require the construction of a ferroelectric capacitor adjacent to, or over, a CMOS transistor. In practice, the CMOS transistors are, constructed on a conventional silicon substrate and then covered with a silicon dioxide layer. The ferroelectric capacitor structures are then constructed on the SiO.sub.2 layer. The ferroelectric capacitor construction requires that a multi-layer structure constructed over the SiO.sub.2 layer be etched back to the SiO.sub.2 layer in selected regions. The multi-layer structure includes layers of platinum and PZT based compounds. The preferred etchant is a dry plasma etch, since such etching systems do not undercut the electrodes of the ferroelectric capacitor.
To etch the ferroelectric oxides of interest, a combination of fluorine and chlorine must be used in the plasma. Such plasma etchants etch SiO.sub.2 much faster than PZT compounds. Hence, any irregularities in the multi-layered structure will be transferred to the underlying SiO.sub.2. Furthermore, these irregularities will be magnified in the process because of the faster etch rates in SiO.sub.2. Such irregularities in the SiO.sub.2 layer cause problems when subsequent metal layers are applied to connect the various components.
Broadly, it is the object of the present invention to provide, an improved method for constructing a device having a ferroelectric layer that must be etched.
It is a further object of the present invention to provide a method for constructing a ferroelectric capacitor that allows the above described multi-layer stack to be etched leaving a flat SiO.sub.2 layer in the etched regions.
It is a still further object of the present invention to provide a method for constructing a ferroelectric capacitor that allows the multi-layer stack to be etched using a dry plasma etch.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.